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ISL6536
Data Sheet December 28, 2004 FN9114.2
Four Channel Supervisory IC
The ISL6536 is a four channel supervisory IC designed to monitor voltages >, = 0.7V. This IC bias range is from 2.7V to 4V but can supervise any positive voltage using an external resistor divider to translate to a lower voltage for comparison to the internal 0.63V reference. Once properly biased and enabled when all four voltage monitor (VMON) inputs are satisfied the PGOOD output will be immediately released to go high to signal that voltage is valid on all four rails. Subsequently when the monitored voltage on any rail drops below its user defined threshold point, the PGOOD output is pulled low. Each rail's VMON point is independently adjustable with a resistor divider. The PGOOD output is guaranteed to be valid with IC bias lower than 1V. The VMON inputs will ignore 30s transients on the monitored supplies. The PGOOD output is an open-drain to allow ORing of multiple signals and interfacing to a range of logic levels. The ENABLE input provides for a reset of the PGOOD output when it is pulled down below 0.5V. With an internal 10uA pull-up to VDD it can be signalled with common logic or pulled to ground with a push button switch.
Features
* Adjustable undervoltage lockout for each supply * Active high PGOOD Output * Guaranteed PGOOD Valid to Falling VDD < 1V * VMON Glitch Immunity * Pb-Free Available (RoHS Compliant)
Applications
* Graphics Cards * Multi voltage DSPs and Processors * P Voltage Monitoring * Embedded Control Systems * Intelligent Instruments * Medical Equipment * Network Routers * Portable Battery-Powered Equipment * Set-Top Boxes
Typical Application Schematic
V4 in V3 in V2 in V1 in
* Telecommunications Systems
Ordering Information
PART NUMBER ISL6536IB ISL6536IBZ (See Note) ISL6536IB-T TEMP. RANGE (C) -40 to +85 -40 to +85 PACKAGE 8 LD SOIC 8 LD SOIC (Pb-free) PKG. DWG. # M8.15 M8.15
ISL6536
*OPT
1 2 3 4
VDD PGD EN GND
VMON1 8 VMON2 7 VMON3 6
8 LD SOIC Tape and Reel 8 LD SOIC (Pb-free)
VMON4 5
ISL6536IBZ-T (See Note)
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2004. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
ISL6536 Pin Descriptions
ISL6536 1 2 PIN NAME VDD PGOOD Bias IC from nominal 2.7V to 4V PGOOD is the boolean AND function of all the UV inputs being satisfied. This is an open drain output and can be pulled high to the appropriate level with an external resistor. Additionally a 20k pull up to VDD is provided internally. Enabling input for supervisory function. Has a 10A pull-up to VDD IC ground These inputs provide for a programmable monitored voltage threshold referenced to an internal 0.63V reference. These inputs have a 30s glitch filter to prevent transient upsets from being recognized by PGOOD. FUNCTION DESCRIPTION
3 4 5-8
ENABLE GND VMON1 VMON2 VMON3 VMON4
VDD
EN
VMON1
10A 20K
VMON2
FALLING EDGE GLITCH FILTER VMON3
PGOOD
VMON4
+ 633mV -
ISL6536
2
FN9114.2 December 28, 2004
ISL6536
Absolute Maximum Ratings
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.5V VMON, PGOOD, ENABLE. . . . . . . . . . . . . . . . . -0.3V to VDD+0.3V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4kV (HBM)
Thermal Information
Thermal Resistance (Typical, Note 1)
JA (C/W)
Operating Conditions
VDD Supply Voltage Range. . . . . . . . . . . . . . . . . . . . . +2.7V to +4V Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . . .-40C to 85C
8 LD SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150C Maximum Storage Temperature Range . . . . . . . . . . . -65C to 150C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board. See Tech Brief TB379 for details. 2. 2. All voltages are relative to GND, unless otherwise specified.
Electrical Specifications
PARAMETER BIAS IC Supply Current VDD Power On VDD Power On Reset PGOOD Pull-Down Current Pull-Up Resistance Output Low Delay from VMON Rising Delay from EN Rising Delay from EN Falling ENABLE Rising Threshold Threshold Hysteresis Pull-up Current VMON Input Falling Threshold Falling Threshold Temp Coeff. Hysteresis Range Glitch Filter Duration
Nominal VDD = 3.3V, TA = TJ = -40C - 85C, Unless Otherwise Specified SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
IVDD VDD_L2H VDD_POR
VMON > VMON_L2H VDD low to high VDD high to low
165 2.6 2.4
1000
A V V
PGpd PGpu
VPGOOD = 0.5V
2 20
mA k 0.1 V s s s
VPGl TPGdelVMON TPGdelENR TPGdelENF
VDD= 1V Last valid input = Vth to PG release EN high to PG release EN low to PG pulling low
0.05 2 0.05 0.015
VEN VEN_HYS IENpu
ENABLE Low to High Threshold
0.4VDD
0.5VDD 0.065
0.6VDD
V V A
VEN = 0.5V
10
3.3VMON_H2L 3.3VMON_TC VVMON_HYS VMON_RNG TFIL
Tj=+25c
0.623
0.633 100
0.643
V uV/C
VMON glitch to PGOOD low Filter -
10 8 30
-
mV mV s
3
FN9114.2 December 28, 2004
ISL6536 ISL6536 Description and Operation
The ISL6536 is a four channel supervisory IC designed to monitor multiple voltages greater than 0.7V. This IC is suitable for both microprocessors or industrial system applications. Upon VDD bias power up the PGOOD output is held low with VDD as low as 0V. Once biased to 2.6V and enabled the IC continuously monitors from one to four voltages independently through external resistor dividers comparing each VMON pin voltage to an internal 0.63V reference. Once all VMON input voltages rise above 0.63V the PGOOD (power good) output signal is released and is pulled high via an external pull resistor to indicate that the power conditions have been met. The PGOOD output is an open-drain to allow ORing of the signals and interfacing to a wide range of logic levels. Once any VMON input falls below 0.63V the PGOOD output is pulled low, the VMON inputs are designed to reject fast transients (30s). If less than four voltages are being monitored, connect the unused VMON pins to VDD. The PGOOD pin has an internal 20k pull-up to VDD making an external pull-up resistor unnecessary. Figure 1 illustrates the operational timing diagram.
4/5 EN/VMON INPUTS HIGH VTH LAST EN/VMON INPUT TFIL PGOOD OUTPUT
FIGURE 1. ISL6536 OPERATIONAL TIMING DIAGRAM
Typical Performance Curves
0.6 0.5 VMONVDD BIAS CURRENT (mA)
0.4 0.3 0.2 0.1 0 2.6 VMON>VMON_L2H
3.0
VDD BIAS VOLTAGE (V)
FIGURE 2. VDD CURRENT vs. VDD VOLTAGE
FIGURE 3. VMON THRESHOLD vs. VDD VOLTAGE
4
FN9114.2 December 28, 2004
ISL6536 Typical Performance Curves
(Continued)
PGOOD
VMON
PGOOD
EN
PG = 1V/DIV EN = 1V/DIV
1s/DIV
PG = 2V/DIV VMON = 1V/DIV
1s/DIV
FIGURE 4. EN HIGH to PGOOD
FIGURE 5. VMON HIGH to PGOOD
VMON
PGOOD EN PGOOD
EN = 1V/DIV PG = 1V/DIV
10nS/DIV
PGOOD = 2V/DIV VMON = 1V/DIV
10s/DIV
FIGURE 6. EN LOW to PGOOD
FIGURE 7. VMON LOW to PGOOD
VMON
PGOOD EN PGOOD
EN = 1V/DIV PG = 1V/DIV
10nS/DIV
PGOOD = 2V/DIV VMON = 1V/DIV
10s/DIV
FIGURE 8. EN LOW to PGOOD
FIGURE 9. VMON LOW to PGOOD
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FN9114.2 December 28, 2004
ISL6536 Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A
L
MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 MAX 1.75 0.25 0.51 0.25 5.00 4.00 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93
MIN 0.0532 0.0040 0.013 0.0075 0.1890 0.1497
MAX 0.0688 0.0098 0.020 0.0098 0.1968 0.1574
A1 B C D E

A1 0.10(0.004) C
e H h L N
0.050 BSC 0.2284 0.0099 0.016 8 0o 8o 0.2440 0.0196 0.050
1.27 BSC 5.80 0.25 0.40 8 0o 6.20 0.50 1.27
e
B 0.25(0.010) M C AM BS
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 6
FN9114.2 December 28, 2004

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